Description: 将1Mhz的频率信号转换成29hz的频率。分频器-Converting the frequency signal into a frequency of 29hz of 1Mhz. Divider Platform: |
Size: 3072 |
Author:何三 |
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Description: 时钟分频器原理与实现，计数跳变的频率和加减模式可实时变化，通过Nano实验板上的LCD显示器显示。计数频率、加减选择和初始化操作通过板上的拨动开关和Reset按钮实现。-Principle and Implementation clock divider, counting and addition and subtraction frequency hopping mode changes in real time, through the LCD display panel show Nano experiments. Counting frequency, subtraction selection and initialization by a toggle switch panel and Reset buttons to achieve. Platform: |
Size: 818176 |
Author:范鹏 |
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Description: 用verilog写的分频器，包括16分频，8分频，4分频，2分频等，代码简单，效率高，个人感觉很实用且对初学者很有帮助-Written in verilog divider, including 16 points frequency, frequency eight points, 4 points frequency, frequency division 2, etc., the code is simple, high efficiency, personal feeling is very practical and is very helpful for beginners Platform: |
Size: 1024 |
Author:张俊 |
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Description: ICST307 VCO frequency must be between 6MHz and 200MHz (3.3 or 5V). This frequency is pre-output divider.
Platform: |
Size: 2048 |
Author:jikengxe |
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Description: 根据血液对光的吸收程度，通过感光器来收集数据，来测试心跳。 TSL235 感光器，放在手指下面，手指上面用光照，从而收集数据。需要配合配件TSL235 感光器，电路板，电阻。-You are going to interface a TSL235 to the FPGA. The TSL235 is a light-to-frequency converter whose
output digital bitstream frequency is directly proportional to the intensity of light. You want to count
the duration edge to edge of a gated input (TSL235) using the 50MHz clk as the stable clk input.
At the end of each period you want to latch the count for display with the green LEDs on the board. For
now you can illuminate the TSL235 with any light source you want. Don t worry about calibrating the
output just use a count of 2^10, or 1024. You can use a simple voltage divider to convert the 5volts
the TSL to 3.3 volts for the FPGA (10k over a 5.1k). Carefully connect the 3.3v the TSL and
the GND to inputs on the GPIO header on the DE0 board. Platform: |
Size: 2569216 |
Author:charles |
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Description: The Slow Peripherals Clock Group includes the McBSPs, I2C, and the UART. The input clock to this clock
group is taken the output of divider 2 (D2). by default, the divider is set to divide its input clock by
four, but the divide value can be changed to divide-by-1 or divide-by-2 by modifying the PLLDIV2 bits of
the PLL Divider2 Register (PLLDIV2) through software. The clock frequency of the Slow Peripherals Clock
Group must be equal to or less than that of the Fast Peripherals Clock Group.-The Slow Peripherals Clock Group includes the McBSPs, I2C, and the UART. The input clock to this clock
group is taken the output of divider 2 (D2). by default, the divider is set to divide its input clock by
four, but the divide value can be changed to divide-by-1 or divide-by-2 by modifying the PLLDIV2 bits of
the PLL Divider2 Register (PLLDIV2) through software. The clock frequency of the Slow Peripherals Clock
Group must be equal to or less than that of the Fast Peripherals Clock Group. Platform: |
Size: 4096 |
Author:ehsan |
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Description: 设计四位定点有符号整数除法器（op=ai÷bi），软件仿真通过后下载到FPGA板子进行验证
[具体要求]
1、 使用clock为输入时钟信号，其频率为50MHz
2、 使用拨码开关sw7~sw4为被除数ai，其中sw7为MSB(高位)，sw4为LSB(低位)
3、 使用拨码开关sw3~sw0为除数bi，其中sw3为MSB，sw0为LSB
4、 使用按钮btn<0>作为输入确定信号，在每次改变输入时按下按钮得到输出结果
5、 以LED7~4为所得商op，LED3为MSB，灯亮代表该位为1.
6、 以LED3~0为所得余数，LED7为MSB
7、 若除数为0，则led7闪烁（闪烁频率自定义，以肉眼能分辨为准），led6~0熄灭
-Design of four sentinel signed integer divider (op = aibi), the software downloaded to the FPGA board through simulation to validate [the specific requirements] 1, using the clock as an input clock signal having a frequency of 50MHz 2, using a DIP switch sw7 ~ sw4 as dividend ai, which sw7 is MSB (high), sw4 for the LSB (low) 3, using DIP switches sw3 ~ sw0 divisor bi, where sw3 is MSB, sw0 for the LSB 4, using the buttons btn < 0> determining the signal as an input, press the Enter button at each change to get the output 5 to LED7 ~ 4 as the quotient op, LED3 is MSB, lights representing the bit is 1.6 to LED3 ~ 0 is the proceeds of the remainder, LED7 the MSB 7, if the divisor is zero, then led7 flashing (frequency custom, to the naked eye can distinguish prevail), led6 ~ 0 Off Platform: |
Size: 4096 |
Author:刘东辉 |
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Description: 时钟分频的verilog代码，能够实现小数分频，文件为Xilinx ISE工程文件-Frequency clock divider verilog codes, it is possible to achieve fractional file to Xilinx ISE Project Files Platform: |
Size: 390144 |
Author:duzengquan |
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Description: 数控分频器的功能就是当在输入端给定不同输入数据时，将对输入的时钟信号有不同的分频比，参考代码中的数控分频器是用可并行预置的加法计数器设计完成的，当加法计数器溢出时进行并行预置。-The function of NC divider is when in the input given different input data, the input clock signal has a different frequency ratio, reference code in the NC divider is parallel to finish the design of the addition counter preset, when the addition counter overflow of parallel presetting. Platform: |
Size: 3072 |
Author:张宇晴 |
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Description: EG8010 is a digital pure sine wave inverter ASIC (Application Specific Integrated Circuit) with
complete function of built-in dead time control. It applies to DC-DC-AC two stage power converter
system or DC-AC single stage low power frequency transformer system for boosting. EG8010 can
achieve 50/60Hz pure sine wave with high accuracy, low harmonic and distortion by external
12MHz crystal oscillator. EG8010 is a CMOS IC that integrates SPWM sinusoid generator, dead
time control circuit, range divider，soft start circuit, circuit protection, RS232 serial communication,
12832 serial LCD unit, and etc. Platform: |
Size: 239616 |
Author:jofre |
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Description: CS5460A 是一个包含两个ΔΣ模-数转换
器（ADC）、高速电能计算功能和一个串行接
口的高度集成的ΔΣ 模-数转换器。 它可以精确
测量和计算有功电能、 瞬时功率、 I
RMS 和VRMS ，
用于研制开发单相2 线或3 线电表。CS5460A
可以使用低成本的分流器或互感器测量电流，使
用分压电阻或电压互感器测量电压。CS5460A
具有与微控制器通讯的双向串口， 芯片的脉冲输
出频率与有功能量成正比。 CS5460A 具有方便
的片上AC/DC 系统校准功能-The CS5460A is a highly integrated power measurement solution which combines two ∆ Σ
Analog-to-Digital Converters (ADCs), high speed
power calculation functions, and a serial interface
on a single chip. It is designed to accurately measure and calculate: Real (True) Energy,
Instantaneous Power, IRMS, and V
RMS for single
phase 2- or 3-wire power metering applications.
The CS5460A interfaces to a low-cost shunt resistor or transformer to measure current, and to a
resistive divider or potential transformer to measure voltage. The CS5460A features a
bi-directional serial interface for communication
with a micro-controller and a pulse output engine
for which the average pulse frequency is proportional to the real power. The CS5460A has on-chip
functionality to facilitate AC or DC system-level
calibration Platform: |
Size: 574464 |
Author:longyong |
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Description: 7段数码管控制接口程序和对初始频率为50MHZ的时钟的分频程序-7-segment control interface program and the initial frequency of 50MHZ clock divider program Platform: |
Size: 1024 |
Author:李康康 |
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Description: （1） Divid 模块：1Hz 分频模块，开发板提供50MHz 的系统时钟，而该设计交通灯
转换以秒为计时单位，对50MHz 分频得到1Hz 脉冲信号。
（2） Divid_200 模块: 200Hz 分频模块,用于产生动态扫描模块的时钟。一个数码管
稳定显示要求的切换频率要大于50Hz，那么4 个数码管则需要50×4＝200Hz 以上
的切换频率才能看到不闪烁并且持续稳定显示的字符，因而扫描频率设定为
200Hz。
（3） Control 模块：A、B 方向红绿灯控制模块，红灯、绿灯为20 秒，黄灯为5 秒。
并实现计时数据转换，即将数据分为十位显示数据，与各位显示数据，用于数码管
显示。
（4） saomiao 扫描模块：轮流选通2 位数码管，实现动态扫描，以显示倒计时数据。-(1) Divid module: 1Hz divider module, the development board provides 50MHz system clock, and the design of traffic lights
Conversion in seconds for the time unit, the 50MHz frequency to be 1Hz pulse signal.
(2) Divid_200 module: 200Hz frequency division module, used to generate the dynamic scanning module clock. A digital tube
Stable display requirements of the switching frequency is greater than 50Hz, then the four digital tubes need 50 × 4 200Hz or more
Of the switching frequency to see the non-flickering and continuous display of the characters, so the scanning frequency is set to
200Hz.
(3) Control module: A, B direction traffic light control module, red, green for 20 seconds, yellow for 5 seconds.
And to achieve timing data conversion, the data is divided into ten display data, and you display data for digital
display.
(4) saomiao scanning module: 2-bit strobe digital control, dynamic scanning to show the countdown data. Platform: |
Size: 533504 |
Author:panda |
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Description: 这是内部有10位ADC的一个简单应用，这个电路最多测量30 V DC，可以应用在台式电源或各种系统中的面板仪表。
PIC16F676的内部adc与一个电阻网络分压器用于测量输入电压，用数码管来显示电压值，频率在50HZ左右
在原理图中的47K看到和10K电位连接分压器配置。在默认情况PIC微控制器ADC参考电压设置到VCC（+ 5V在这种情况下），分出最大射程30伏到5伏这样的分压器。(This is a simple application with 10 bit ADC inside. This circuit measures at most 30 V DC, and can be used in desktop power supply or panel meters in various systems.
PIC16F676 internal ADC and a resistor network divider used to measure the input voltage, digital tube to display voltage values, the frequency is about 50HZ
In the schematic, the 47K is seen and the 10K potential is connected to the voltage divider configuration. By default, the PIC microcontroller ADC reference voltage is set to VCC (+ 5V in this case), dividing the maximum range from 30 volts to 5 volts for such a voltage divider.) Platform: |
Size: 6144 |
Author:华仔华仔
|
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